1. Field of the Invention
The present invention relates to a circuit for making a comparison between sizes of two numeric data in a microprocessor or the like, and to be further detailed, relates to a size comparing circuit capable of finding the compared result in a shorter processing time in comparison with the conventional ones.
2. Description of the Prior Art
FIG. 1 is a block diagram showing an example of configuration of a size comparing circuit carrier in "Principles of CMOS VLSI Design", p. 333-335, by Neil H. E. Weste and Kamran Eshraghian.
In FIG. 1, numerals 53a, 53b, 53c, 53d and 53e designate full adders respectively, which are connected in a carry-series manner that an output terminal Co of each adder is connected sequentially to a carry input terminal Ci of the following stage.
Also, in FIG. 1, symbols A.sub.3, A.sub.2, A.sub.1 A.sub.0 and B.sub.3, B.sub.2, B.sub.1, B.sub.0 designate respective bits of data DA and DB of natural binary number whose MSBs (Most Significant Bit) are A.sub.3 and B.sub.3 respectively. Then, the LSB (Least Significant Bit) A.sub.0 of the data DA is inputted to one of data input terminals a.sub.1 of the first full adder 53a, and the LSB B.sub.0 of the data DB inverted by an inverter 52a is inputted to the other data input terminal a.sub.2.
Furthermore, the respective bits A.sub.1, A.sub.2, A.sub.3 and B.sub.1, B.sub.2, B.sub.3 of the both data DA and DB are inputted sequentially to both data input terminals of each of the other full adders 53b, 53c and 53d respectively.
In addition, a power source voltage, that is, a binary code "1" is inputted to the carry input Ci of the first full adder 53a, a ground voltage, that is, a binary code "0" is inputted to the first data input terminal a.sub.1 of the fifth full adder 53e, and the power source voltage, that is, the binary code "1" is inputted to the second data input terminal a.sub.2 of the same, respectively.
Also, output signals S.sub.0, S.sub.1, S.sub.2, S.sub.3 and S.sub.s of the respective full adders 53a, 53b, 53c, 53d and 53e are respective bits of an added result signal wherein S.sub.s is a sign bit representing "+" or "-".
Such a conventional size comparing circuit is operated as follows.
To make a size comparison between natural binary numbers, a sign bit is added to each natural binary number, and subtraction is performed as binary numbers expressed by twos complement, and judgment has only to be made on whether the result of the subtraction is positive or negative. Also, subtraction of binary numbers of twos complement expression by the full adder is given by (A+B+1); where A is minuend and B is subtrahend. Note that B is an inverted value of B, that is, if B is "1", B is "0", and if B is "0", B is "1".
FIG. 1 is a circuit for realizing the above-described processing, the sign bit "0" to be added to the natural binary number DA (A.sub.3 A.sub.2 A.sub.1 A.sub.0) is inputted by a "0" input to the first data input terminal a.sub.1 of the fifth full adder 53e, and the respective bits B.sub.0 to B.sub.3 of the data DB are inverted by inverters 52a to 52d, and are inputted as B.sub.0 to B.sub.3, respectively. Also, the sign bit "0" to be added to the natural binary number DB (B.sub.3 B.sub.2 B.sub.1 B.sub.0) are inverted to "1" and is inputted by a "1" input to the second data input terminal a.sub.2 of the fifth full adder 53e.
Then, since "1" has been inputted to the carry input Ci of the first full adder 53a, subtraction is performed by inputting the respective bits of A.sub.3, A.sub.2, A.sub.1, A.sub.0 and B.sub.3, B.sub.2, B.sub.1, B.sub.0 of the natural binary numbers DA and DB and thereby the result is obtained as a binary number (S.sub.s S.sub.3 S.sub.2 S.sub.1 S.sub.0) of twos complement expression.
At this time, it can be judged that which natural binary number is larger by the sign bit S.sub.s of the fifth full adder.
This means that
If S.sub.s ="0", DA(A.sub.3 A.sub.2 A.sub.1 A.sub.0).gtoreq.DB(B.sub.3 B.sub.2 B.sub.1 B.sub.0), and
If S.sub.s ="1", DA(A.sub.3 A.sub.2 A.sub.1 A.sub.0)&lt;DB(B.sub.3 B.sub.2 B.sub.1 B.sub.0).
Accordingly, the size comparison between two natural binary numbers can be made by the circuit shown in FIG. 1.
In the conventional size comparing circuit as described above, a large number of full adders are required, and therefore such deficiencies exist as that the circuit configuration is complicated and the circuit scale is made larger, and further the processing time is extended since processing is required to be performed on all the bits of data to be processed in order to obtain the result. This problem of processing time, needless to say, becomes more serious with increase in the number of bits of data.